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general description the MAX14808/max14809 octal three-level/quad five- level, high-voltage (hv) pulser devices generate high- frequency hv bipolar pulses (up to q 105v) from low- voltage control logic inputs for driving piezoelectric transducers in ultrasound systems. all eight channels have embedded overvoltage-protection diodes and an integrated active return-to-zero clamp. both devices have embedded independent (floating) power supplies (fps) and level shifters that allow signal transmission without the need for external hv capacitors. the MAX14808 also features eight integrated transmit/receive (t/r) switches. the max14809 does not have the t/r switch function. the devices feature two modes of operation: an octal three-level pulser mode (with integrated active return- to-zero clamp) or a quad five-level pulser mode. in octal three-level pulser mode, each channel is controlled by two logic inputs (dinn_ /dinp_) and the active return to zero features half the current driving of the pulser 1a (typ). in quad five-level pulser mode, each channel is controlled by three logic inputs and the active return to zero has the same current driving of the pulser 2a (typ). the devices can operate both in clocked and transparent mode. in clocked mode, data inputs can be synchronized with a clean differential or single-ended clock to reduce phase noise associated with fpga output signals that are detrimental for doppler analysis. in transparent mode, the synchronization feature is disabled and output reflects the data input after a 18ns delay. both devices feature adjustable maximum current (0.5a to 2a) to reduce power consumption when full current capability is not required. the devices feature integrated grass-clipping diodes (with low parasitic capacitance) for receive (rx) and transmit (tx) isolations. both devices feature a damping circuit that can be activated as soon as the transmit burst is over. the damping circuit has a typical on-resistance of 500 i . it fully discharges the pulsers output internal node before the grass-clipping diodes. the devices are available in a 68-pin (10mm x 10mm) tqfn package with an exposed pad and are specified over the -40 n c to +85 n c extended temperature range. benefits and features s save space (optimized for high-channel-count systems/portable systems) ? high density ? eight channels (three-level operation) ? four channels (five-level operation) in one package ? integrated low-power t/r switches (MAX14808) ? directdrive ? architecture eliminates external high-voltage capacitor ? no external floating power supply (fps) required s high performance (designed to enhance image quality) ? excellent -43dbc (typ) thd for second harmonic at 5mhz ? sync function eliminates effects of fpga jitter and improves performance in doppler mode ? low propagation delay 18ns (typ) ? strong active return to zero s save power ? low quiescent power dissipation (5.7mw/ channel in octal mode) ? programmable current capability ? shutdown mode and disable transmit mode applications ultrasound medical imaging industrial flaw detection piezoelectric drivers test equipment 19-6438; rev 0; 9/12 ordering information and functional diagram appear at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14808.related . directdrive is a registered trademark of maxim integrated. MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 (all voltages referenced to gnd.) v dd logic supply voltage range ....................... -0.3v to +5.6v v cc positive driver supply voltage range ......... -0.3v to +5.6v v ee negative driver supply voltage range ........ -5.6v to +0.3v v nna , v nnb high negative supply voltage range ..................................... -110v to +0.3v v ppa , v ppb high positive supply voltage range ..................................... -0.3v to +110v out_ output voltage range ................................. v nn_ to v pp_ lvout_ output voltage range (100ma maximum current)........ ...................... -1.2v to +1.2v dinn_, dinp_, cc_, sync, ldo_en .................. -0.3v to +5.6v clk, clk , mode_ voltage range .......... -0.3v to (v cc + 0.3v) thp logic output voltage range ........................ -0.3v to +5.6v v gpa , v gpb output voltage range ....... max[(v pp_ - 5.6v), (v ee + 0.6v)] to (v pp_ + 0.3v) v gna , v gnb output voltage range ...... (v nn_ - 0.3v) to min[(v cc + 0.6v), (v nn_ + 5.6v)] continuous power dissipation (t a = +70c) tqfn (derate 50mw/ n c above +70c) ...................... 4000mw operating temperature range .......................... -40c to +85c maximum junction temperature ..................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................ +300c lead temperature (reflow) .............................................. +260c tqfn junction-to-ambient thermal resistance ( b ja ) ............ 20c/w junction-to-case thermal resistance ( b jc ) .................. 0.5c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) dc electrical characteristics (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units power supplies (v dd , v cc , v ee , v pp_ , v nn _) logic supply voltage v dd +1.7 +3 +5.25 v positive drive supply voltage v cc +4.9 +5 +5.1 v negative drive supply voltage v ee -5.1 -5 -4.9 v high-side supply voltage v pp_ 0 +105 v low-side supply voltage v nn_ -105 0 v external low-side ldo voltage v gn_ - v nn_ ldo_en = high 5 5.3 5.5 v external high-side ldo voltage v pp_ - v gp_ ldo_en = high 5 5.3 5.5 v external floating power-supply current from v gn_ i vgn_ ldo_en = high (note 3) 50 ma external floating power-supply current from v gp_ i vgp_ ldo_en = high (note 3) 85 ma logic inputs/outputs (dinn_, dinp_, mode_, sync, cc_, ldo_en ) low-level input threshold v il 0.2 x v dd v high-level input threshold v ih 0.8 x v dd v logic input capacitance c in 4 pf maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
3 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units logic input leakage (all inputs except ldo_en ) i in v in = 0v or v dd -1 0 + 1 f a ldo_en pulldown resistance r ldo_en 7 10 14 k i thp low-level output voltage v ol pullup resistor to v dd (r pullup = 1k i ) 0.1 x v dd v clock inputs (clk, clk )differential mode differential clock input voltage range v clkd 0.2 2 v p-p common-mode voltage v clkcm v cc /2 v common-mode voltage range v cl v cc /2 - 0.45 v cc /2 + 0.45 v input resistance r clk , r clk differential 7 k i common mode 23 k i input capacitance c clk , c clk capacitance to gnd (each input) 4 pf clock inputs (clk, clk )single-ended mode (v clk < 0.1v) low-level input v il clk 0.2 x v dd v high-level input v ih clk 0.8 x v dd v single-ended mode selection threshold low v il clk 0.1 v single-ended mode selection threshold high v ih clk 1 v input capacitance (clk) c clk 4 pf logic input leakage (clk) i clk v clk = 0v or v dd -1 0 +1 f a pullup current ( clk ) i clk v clk = 0v 120 180 f a supply currentshutdown mode (mode0 = low, mode1 = low) v dd supply current i dd all inputs connected to gnd or v dd 3 f a v cc supply current i cc all inputs connected to gnd or v dd 22 f a v ee supply current i ee all inputs connected to gnd or v dd 13 f a v pp_ supply current i pp_ all inputs connected to gnd or v dd 10 f a v nn_ supply current i nn_ all inputs connected to gnd or v dd 10 f a supply currentdisable mode (mode0 = high, mode1 = high) v dd supply current i ddq all inputs connected to gnd or v dd transparent or single- ended clock mode 1.7 3 f a differential clock mode, v clkd = 0.2v 110 190 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
4 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units v ee supply current i eeq dinn_ = dinp_ = gnd 0.26 0.4 ma dinn_ = dinp_ = v dd MAX14808 9.4 13 max14809 1.37 2 v cc supply current i ccq dinn_ = dinp_ = gnd 0.49 0.75 ma dinn_ = dinp_ = v dd MAX14808 9.6 13.2 max14809 1.6 2.3 v cc supply current increase in clocked mode d i cc differential clock mode 3.5 5 ma v nn_ total supply current (quiescent mode) i nnq_ all inputs connected to gnd or v dd 195 305 f a v pp_ total supply current (quiescent mode) i ppq_ all inputs connected to gnd or v dd 220 340 f a total power dissipation per channel (disable mode) p pdis1 t/r switch off, damp off (transparent mode) 5.7 mw p pdis2 dinn_ = dinp_ = v dd MAX14808 17 max14809 7 supply currentoctal three-level mode, no load (mode0 = high, mode1 = low) v dd supply current (quiescent mode) i dd all inputs connected to gnd or v dd transparent or single-ended clock mode 1.7 3 f a differential clock mode, v clkd = 0.2v 110 190 v ee supply current (quiescent mode) i eeq dinn_ = dinp_ = gnd 0.26 0.4 ma dinn_ = dinp_ = v dd MAX14808 9.4 13 max14809 1.37 2 v cc supply current (quiescent mode) i ccq dinn_ = dinp_ = gnd 0.49 0.75 ma dinn_ = dinp_ = v dd MAX14808 9.6 13.2 max14809 1.6 2.3 v cc supply current increase in clocked mode d i cc differential clock mode 3.5 5 ma v nn_ total supply current (quiescent mode) i nnq_ all inputs connected to gnd or v dd 195 305 f a v pp_ total supply current (quiescent mode) i ppq_ all inputs connected to gnd or v dd 220 340 f a maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
5 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units total power dissipation per channel (quiescent mode) p pdis1 t/r switch off, damp off (transparent mode) 5.7 mw p pdis2 dinn_ = dinp_ = v dd (transparent mode) MAX14808 17 max14809 7 v dd supply current i dd1 cw doppler (note 4), transparent or single-ended clock mode 2.2 3.2 ma i dd2 b mode (note 5), transparent or single- ended clock mode (figure 1a) 3.3 6 f a v ee supply current i ee1 8 channels switching, cw doppler (note 4) cc0 = high, cc1 = high 67 92 ma i ee2 8 channels switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low MAX14808 9.7 14.8 max14809 1.6 2.6 v cc supply current i cc1 8 channels switching, cw doppler (note 4) cc0 = high, cc1 = high 45 60 ma i cc2 8 channels switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low MAX14808 10 15 max14809 1.8 2.8 v dd supply current increase in clocked mode d i dd differential clock mode 1.8 ma v cc supply current increase in clocked mode d i cc differential clock mode 3.8 ma v nn_ supply current i nn1 8 channels switching, cw doppler, cc0 = high, cc1 = high, r l = 1k i , c l = 240pf (note 4) 157 200 ma i nn2 8 channels switching, b mode (figure 1a), cc0 = low, cc1 = low, r l = 1k i , c l = 240pf (note 5) 2 2.8 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
6 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units v pp_ supply current i pp1 8 channels switching, cw doppler, cc0 = high, cc1 = high, r l = 1k i , c l = 240pf (note 4) 186 230 ma i pp2 8 channels switching, b mode (figure 1a), cc0 = low, cc1 = low, r l = 1k i , c l = 240pf (note 5) 3.1 4.5 power dissipation per channel (octal three-level mode) pd cw 1 channel switching, cw doppler (note 4) 286 mw pd pw 1 channel switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low, r l = 1k i , c l = 240pf MAX14808 73 max14809 66 supply currentquad five-level dual mode, no load (mode0 = low, mode1 = high) v dd supply current (quiescent mode) i ddq all inputs connected to gnd or v dd transparent or single-ended clock mode 1.7 3 f a differential clock mode, v clkd = 0.2v 110 190 v ee supply current (quiescent mode) i eeq dinn_ = dinp_ = gnd 0.26 0.4 ma dinn_ = dinp_ = v dd MAX14808 5.4 7.7 max14809 1.35 2 v cc supply current (quiescent mode) i ccq dinn_ = dinp_ = gnd 0.49 0.75 ma dinn_ = dinp_ = v dd MAX14808 5.6 7.8 max14809 1.6 2.3 v cc supply current increase d i cc differential clock mode 3.5 5 ma v nn_ supply current (quiescent mode) i nnq_ all inputs connected to gnd or v dd 195 305 f a v pp_ supply current (quiescent mode) i ppq_ all inputs connected to gnd or v dd 220 340 f a power dissipation per channel (quiescent mode) p pdis1 t/r switch off, damp off (transparent mode) 11.3 mw p pdis2 dinn_ = dinp_ = v dd (transparent mode) MAX14808 24.1 max14809 14.1 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
7 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units v dd supply current i dd1 4 channels switching, cw doppler (note 4) 1.4 ma i dd2 4 channels switching, b mode (note 5) (figure 1a) 4.3 f a v ee supply current i ee1 4 channels switching, cw doppler (note 4) cc0 = high, cc1 = high 33 ma i ee2 4 channels switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low MAX14808 5.9 max14809 1.6 v cc supply current i cc1 4 channels switching, cw doppler (note 4) cc0 = high, cc1 = high 22 ma i cc2 4 channels switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low MAX14808 6 max14809 1.8 v dd supply current increase d i dd differential clock mode 1.8 ma v cc supply current increase d i cc differential clock mode 3.8 ma v nn_ supply current i nn1 4 channels switching, cw doppler (note 4) cc0 = high, cc1 = high, r l = 1k i , c l = 240pf 90 ma i nn2 4 channels switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low 1.3 v pp_ supply current i pp1 4 channels switching, cw doppler (note 4) cc0 = high, cc1 = high, r l = 1k i , c l = 240pf 103 ma i pp2 4 channels switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low 2.2 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
8 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units total power dissipation per channel (quad five-level dual mode) pd cw 1 channel switching, cw doppler (note 4), r l = 1k i , c l = 240pf 311 mw pd pw 1 channel switching, b mode (note 5) (figure 1a), cc0 = low, cc1 = low, r l = 1k i , c l = 240pf MAX14808 102 max14809 92 supply currentoctal three-level, no load (mode0 = high, mode1 = low, ldo_en = high, v pp_ - v gp_ = +5v, v gn_ - v nn_ = +5v) v ee supply current (quiescent mode) i eeq_ all inputs connected to gnd 25 46 f a v cc supply current (quiescent mode) i ccq_ all inputs connected to gnd 280 420 f a v nn_ supply current (quiescent mode) i nnq_ all inputs connected to gnd 40 62 f a v pp_ supply current (quiescent mode) i ppq_ all inputs connected to gnd 40 62 f a output stage v nna, v nnb connected low- side output impedance r ols i out_ = -50ma cc0 = low, cc1 = low 8.5 i cc0 = low, cc1 = high 10 cc0 = high, cc1 = low 13.5 cc0 = high, cc1 = high 26 48 v ppa, v ppb connected high- side output impedance r ohs i out_ = +50ma cc0 = low, cc1 = low 9 i cc0 = low, cc1 = high 10.5 cc0 = high, cc1 = low 14.5 cc0 = high, cc1 = high 27 53 clamp nfet output impedance r ong i out_ = -50ma, 13.5 i clamp pfet output impedance r opg i out_ = +50ma 13.5 i active damp output impedance r damp before grass-clipping diode 500 i maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
9 dc electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, 1 f f bypass capacitor between v gna and v nna , 1 f f bypass capacitor between v gnb and v nnb , 1 f f bypass capacitor between v gpa and v ppa , 1 f f bypass capacitor between v gpb and v ppb , v ldo_en = 0v, no load, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units v nna, v nnb connected low- side output current i ols v ds = +100v cc0 = low, cc1 = low 2.0 a cc0 = low, cc1 = high 1.5 cc0 = high, cc1 = low 1.0 cc0 = high, cc1 = high 0.5 v ppa, v ppb connected high- side output current i ohs v ds = +100v cc0 = low, cc1 = low 2.0 a cc0 = low, cc1 = high 1.5 cc0 = high, cc1 = low 1.0 cc0 = high, cc1 = high 0.5 gnd-connected nfet output current i ong v ds = +100v 1 a gnd-connected pfet output current i opg v ds = +100v 1 a diode voltage drop (blocking diode and grass-clipping diode) v drop i out_ = q 50ma 1.7 v lvout_diode clamping voltage lv clamp i load = 1ma (MAX14808 only) -0.9 +1 v grass-clipping diode reverse capacitance c rev 2.5 pf out_ equivalent large-signal shunt capacitance c hs 200v p-p signal 80 pf t/r switch on impedance r on MAX14808 only 11.5 i t/r switch off impedance r off MAX14808 only 1 m i lvout_ output offset lv off lvout_, out_ unconnected, v cc = +5v, v ee = -5v -40 0 +40 mv thermal shutdown thermal-shutdown threshold t sdn temperature rising +145 n c thermal-shutdown hysteresis t hys 20 n c maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
10 ac electrical characteristics (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, v gna connected to v nna with 1 f f capacitor, v gnb connected to v nnb with 1 f f capacitor, v gpa connected to v ppa with 1 f f capacitor, v gpb connected to v ppb with 1 f f capacitor, v ldo_en = 0v, v cc0 = 0v, v cc1 = 0v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units logic input to output rise propagation delay t plh from 50% dinp_/dinn_ (transparent mode) to 10% out_ transition swing (figure 2a) 18 ns logic input to output fall propagation delay t phl from 50% dinp_/dinn_ (transparent mode) to 10% out_ transition swing (figure 2a) 18 ns logic input to output rise to gnd propagation delay t pl0 from 50% dinp_/dinn_ (transparent mode) to 10% out_ transition swing (figure 2a) 18 ns logic input to output fall to gnd propagation delay t ph0 from 50% dinp_/dinn_ (transparent mode) to 10% out_ transition swing (figure 2a) 18 ns out_ fall time (v ppa to v nna, v ppb to v nnb ) t fpn (figure 2b) 30 48 ns out_ rise time (v nna to v ppa, v nnb to v ppb ) t rnp (figure 2b) 30 48 ns out_ rise time (gnd to v ppa, gnd to v ppb ) t r0p (figure 2b) 15 22.5 ns out_ fall time (gnd to v nna, gnd to v nnb ) t f0n (figure 2b) 15 22.5 ns out_ rise time (v nna to gnd , v nnb to gnd) t rn0 20% to 80% transition (figure 2b) three-level mode 21 ns five-level dual mode 13 out_ fall time (v ppa to gnd , v ppb to gnd) t fp0 20% to 80% transition (figure 2b) three-level mode 21 ns five-level dual mode 13 t/r switch turn-on time (MAX14808) t ontrsw (figure 3) 0.65 1.2 f s t/r switch turn-off time (MAX14808) t offtrsw (figure 3) (note 6) 0.02 0.1 f s output enable time (shutdown mode to normal operation) t en1 100 f s output disable time (normal operation to shutdown mode) t dis1 10 f s maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
11 ac electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, v gna connected to v nna with 1 f f capacitor, v gnb connected to v nnb with 1 f f capacitor, v gpa connected to v ppa with 1 f f capacitor, v gpb connected to v ppb with 1 f f capacitor, v ldo_en = 0v, v cc0 = 0v, v cc1 = 0v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units output enable time (transmit disable mode to normal operation) t en2 50 ns output disable time (normal operation to transmit disable mode) t dis2 65 ns output enable time (normal operation to sync mode) t en3 4 f s output disable time (sync mode to normal operation) t dis3 500 ns clk frequency f clk 160 mhz input setup time (dinn_, dinp_) t setup 3 ns input hold time (dinn_, dinp_) t hold 3 ns second-harmonic distortion (low voltage) thd2lv f out_ = 5mhz, v ppa = -v nna = +5v, v ppb = -v nnb = +5v, square wave (all modes) -40 dbc second-harmonic distortion (high voltage) thd2hv f out_ = 5mhz, v ppa = -v nna = +100v, v ppb = -v nnb = +100v, square wave (all modes) -43 dbc pulse cancellation pc1 f out_ = 5mhz, v ppa = -v nna = +100v, v ppb = -v nnb = +100v, 2 periods, all harmonics of the summed signed with respect to the carrier -40 dbc pc2 f out_ = 5mhz, v ppa = -v nna = +100v, v ppb = -v nnb = +100v, 2 periods, [(v 0 + v 180 ) rms /(2 x v 0rms )] db -40 pulser bandwidth bw v pp = +60v, v nna = -60v (figure 4) 20 mhz rms output jitter t j f out_ = 5mhz, v ppa = -v nna = +5v, v ppb = -v nnb = +5v, both in clocked mode or transparent mode (figure 5) 6.25 ps maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
12 timing diagrams note 2: all devices are 100% production tested at t a = +85 n c. limits over the operating temperature range are guaranteed by design. note 3: maximum operating current from v gn_ and v gp_ external power sources can vary depending on application requirements. the suggested minimum values assume 8 channels running in continuous transmission (cwd) at 5mhz with cc0 = cc1 = high. note 4: cw doppler: continuous wave, f = 5mhz, v dd = +3v, v cc = -v ee = +5v, v pp_ = -v nn_ = +5v. note 5: b mode: f = 5mhz, prf = 5khz, 1 period, v dd = +3v, v cc = -v ee = +5v, v pp_ = -v nn_ = +100v. note 6: t/r switch turn-off time is the time required to switch off the bias current of the t/r switch. the off-isolation is not guaranteed. figure 1a. high-voltage burst test (three levels) ac electrical characteristics (continued) (v dd = +3v, v cc = +5v, v ee = -5v, v ppa = +100v, v nna = -100v, v ppb = +100v, v nnb = -100v, v gna connected to v nna with 1 f f capacitor, v gnb connected to v nnb with 1 f f capacitor, v gpa connected to v ppa with 1 f f capacitor, v gpb connected to v ppb with 1 f f capacitor, v ldo_en = 0v, v cc0 = 0v, v cc1 = 0v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units t/r switch harmonic distortion (MAX14808) thd trsw r load = 200 i , v signal = 100mv p-p -50 db t/r switch turn-on/off voltage spike (MAX14808) v spike r load = 1k i at both sides of t/r switch 50 mv crosstalk ct f = 5mhz, adjacent channels, r lout_ = 200 i -51 db v ppa = v ppb 200ns v nna = v nnb 200s maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
13 figure 1b. high-voltage burst test (five levels) figure 2a. propagation delay timing v ppa v ppb v nna v nnb 200ns 200s 200ns 200ns out_ dinp_ dinn_ v pp _ gnd v nn _ v dd gnd v dd gnd 10% 50% 50% 50% 50% t ph0 t plh t phl t pl0 10% 10% 10% maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
14 figure 2b. output rise/fall timing figure 3. t/r switch turn-on/off time out_ v pp _ gnd v nn _ t rop t rnp t fpn t fpo 80% 80% 20% 80% 80% 20% 80% 80% 20% 80% 20% 80% t fon t rno MAX14808 dinp_ v dd v rif r l = 1k i r l = 1k i dinn_ 0v ~0v ~v nn_ dinp_ lvout_ out_ v dd v ri f /( 2 x r l + r on ) x (r on + r l ) v ri f /( 2 x r l + r on ) x r l lvout_ out_ t ontrsw t offtrsw maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
15 figure 4. bandwidth v dd v dd v ppa /v ppb v nna /v nnb gnd gnd gnd dinp_ dinn_ 90% v ppa /v ppb 90% v nna /v nnb maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
16 figure 5. jitter timing typical operating characteristics (v dd = +5v, v cc = +5v, v ee = -5v, v pp_ = +100v, v nn_ = -100v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) v dd v dd v ppa /v ppb v nna /v nnb gnd gnd dinp_ dinn_ out_ t dr t jr = dt dr 50% 50% 50% 50% t df t jf = dt df v pp (v) i pp (a) 80 60 40 20 50 100 150 200 250 300 0 0 100 i pp quiescent current vs. v pp MAX14808 toc01 v pp = -v nn three-level mode v nn (v) i nn (a) -20 -40 -60 -80 -250 -200 -150 -100 -50 0 -300 -100 0 i nn quiescent current vs. v nn MAX14808 toc02 v pp = -v nn three-level mode temperature (c) i pp (a) 60 35 10 -15 50 100 150 200 250 300 0 -40 85 i pp quiescent current vs. temperature MAX14808 toc03 three-level mode maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
17 typical operating characteristics (continued) (v dd = +5v, v cc = +5v, v ee = -5v, v pp_ = +100v, v nn_ = -100v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) temperature (c) i nn (a) 60 35 10 -15 -250 -200 -150 -100 -50 0 -300 -40 85 i nn quiescent current vs. temperature MAX14808 toc04 three-level mode i cc quiescent current vs. temperature MAX14808 toc05 temperature (c) i cc (ma) 60 35 -15 10 0.1 0.2 0.3 0.4 0.6 0.5 0.7 0.8 0 -40 85 three-level mode temperature (c) i ee (a) 60 35 10 -15 -250 -200 -150 -100 -50 0 -300 -40 85 i ee quiescent current vs. temperature MAX14808 toc06 three-level mode low to high transition voltage spike MAX14808 toc07 lvout 1ki to gnd out_ 50v/div lvout 1v/div 0v 1s/div high to low transition spike MAX14808 toc08 lvout 1ki to gnd out_ 50v/div lvout 1v/div 0v 1s/div frequency (mhz) thd2 (dbc) 80 60 40 20 -50 -40 -30 -20 -10 0 -60 0 100 thd2 vs. frequency MAX14808 toc09 v pp = -v nn = 100v maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
18 typical operating characteristics (continued) (v dd = +5v, v cc = +5v, v ee = -5v, v pp_ = +100v, v nn_ = -100v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) i pp vs. frequency MAX14808 toc13 frequency (mhz) i pp (ma) 8 6 4 2 50 100 150 200 250 300 350 400 450 500 0 01 0 v pp = -v nn = 5v cc0 = cc1 = high 4 channels switching pulse cancellation MAX14808 toc11 out_ wave 1 50v/div out_ wave 2 50v/div sum of wave 1 and 2 3v/div 0v 80ns/div pulse cancellation fft MAX14808 toc12 out_ wave 1 50v/div out_ wave 2 50v/div out_wave 1 20db/div sum of wave 1 and 2 20db/div 0v 80ns/div v pp (v) thd2 (dbc) 80 60 40 20 -50 -40 -30 -20 -10 0 -60 0 100 thd2 vs. v pp MAX14808 toc10 v pp = -v nn f = 5mhz maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
19 typical operating characteristics (continued) (v dd = +5v, v cc = +5v, v ee = -5v, v pp_ = +100v, v nn_ = -100v, r l = 1k i , c l = 240pf, unless otherwise noted. typical values are at t a = +25c.) i nn vs. frequency MAX14808 toc14 frequency (mhz) i nn (ma) 8 6 4 2 450 400 350 300 250 200 150 100 50 0 500 01 0 v pp = -v nn = 5v cc0 = cc1 = high 4 channels switching i cc vs. frequency MAX14808 toc15 frequency (mhz) i cc (ma) 8 6 4 2 10 20 30 40 50 60 70 80 90 100 0 01 0 v pp = -v nn = 5v cc0 = cc1 = high 4 channels switching i ee vs. frequency MAX14808 toc16 frequency (mhz) i ee (ma) 8 6 4 2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 01 0 v pp = -v nn = 5v cc0 = cc1 = high 4 channels switching output jitter MAX14808 toc17 in out propagation delay jitter std = 6.24ps 10ps/div f = 5mhz v pp = 5v 20/div maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
20 pin configurations tqfn (10mm x 10mm x 0.75mm) 18 20 19 21 22 23 24 25 26 27 28 29 30 31 gnd + v dd dinp5 *ep dinn5 dinp6 dinn6 dinp7 dinn7 dinp8 dinn8 v cc v ee v gnb v gpb gnd *connect ep to gnd v dd dinp1 dinn1 dinp2 dinn2 dinp3 dinn3 dinp4 dinn4 v cc v ee v gna v gpa v ppa gnd v nna 60 59 58 57 56 55 66 65 68 67 64 63 62 61 1 234 56 78 91 01 11 21 31 4 51 50 49 48 47 46 45 44 43 42 41 40 39 38 mode0 mode1 lvout5 lvout6 lvout7 lvout8 cc1 cc0 clk clk sync thp lvout4 lvout3 lvout2 lvout1 v ppb out6 v nnb out8 out7 v ppb out5 v nnb gnd v nna out4 v ppa out3 v nna out2 v ppa out1 15 16 17 37 36 35 32 v ppb 33 gnd 34 v nnb 54 53 52 ldo_en top view MAX14808 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
21 pin configurations (continued) tqfn (10mm x 10mm x 0.75mm) *connect ep to gnd 18 20 19 21 22 23 24 25 26 27 28 29 30 31 gnd + v dd dinp5 *ep dinn5 dinp6 dinn6 dinp7 dinn7 dinp8 dinn8 v cc v ee v gnb v gpb gnd v dd dinp1 dinn1 dinp2 dinn2 dinp3 dinn3 dinp4 dinn4 v cc v ee v gna v gpa v ppa gnd v nna 60 59 58 57 56 55 66 65 68 67 64 63 62 61 1 234 56 78 91 01 11 21 31 4 51 50 49 48 47 46 45 44 43 42 41 40 39 38 mode0 mode1 i.c. i.c. i.c. i.c. cc1 cc0 clk clk sync thp i.c. i.c. i.c. i.c. v ppb out6 v nnb out8 out7 v ppb out5 v nnb gnd v nna out4 v ppa out3 v nna out2 v ppa out1 15 16 17 37 36 35 32 v ppb 33 gnd 34 v nnb 54 53 52 ldo_en max14809 top view maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
22 pin description pin name function MAX14808 max14809 1 lvout1 low-voltage t/r switch output 1 2 lvout2 low-voltage t/r switch output 2 3 lvout3 low-voltage t/r switch output 3 4 lvout4 low-voltage t/r switch output 4 1C4, 14C17 i.c. internally connected. connect i.c. to gnd externally. 5 5 ldo_en internal supply generator control input. drive ldo_en high to disable the internal power supply when using an external power supply on v gpa , v gpb , v gna , and v gnb . ldo_en has an internal 10k i pulldown resistor to gnd. 6 6 thp open-drain thermal-protection output. thp asserts and sinks a 3ma current to gnd when the junction temperature exceeds +150 n c. 7 7 sync cmos control input. drive sync high to enable clocked-input mode. drive sync low to operate in transparent mode (see the truth tables section). 8 8 clk cmos control input. clock positive phase input. data inputs are clocked in at the rising edge of clk and clk in differential clocked mode or at the rising edge of clk in single-ended clocked mode. clock maximum frequency is 160mhz. 9 9 clk cmos control input. clock negative phase input. data inputs are clocked in at the edge of clk and clk in differential clocked mode. clock maximum frequency is 160mhz. if clk is connected to gnd, the clk input is a single-ended logic-level clock input. otherwise, clk and clk are self-biased differential clock inputs. 10 10 cc0 current control input. control current capability (see the truth tables section). 11 11 cc1 current control input. control current capability (see the truth tables section). 12 12 mode0 mode control input. control operation mode (see the truth tables section). 13 13 mode1 mode control input. control operation mode (see the truth tables section). 14 lvout5 low-voltage t/r switch output 5 15 lvout6 low-voltage t/r switch output 6 16 lvout7 low-voltage t/r switch output 7 17 lvout8 low-voltage t/r switch output 8 18, 33, 43, 53, 68 18, 33, 43, 53, 68 gnd ground 19, 67 19, 67 v dd logic supply voltage. bypass v dd (both pins) to gnd with a 0.1 f f capacitor as close as possible to the device. 20 20 dinp5 digital signal positive input 5 (see the truth tables section) 21 21 dinn5 digital signal negative input 5 (see the truth tables section) 22 22 dinp6 digital signal positive input 6 (see the truth tables section) 23 23 dinn6 digital signal negative input 6 (see the truth tables section) 24 24 dinp7 digital signal positive input 7 (see the truth tables section) 25 25 dinn7 digital signal negative input 7 (see the truth tables section) 26 26 dinp8 digital signal positive input 8 (see the truth tables section) 27 27 dinn8 digital signal negative input 8 (see the truth tables section) maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
23 pin description (continued) pin name function MAX14808 max14809 28, 58 28, 58 v cc v cc supply voltage. bypass v cc (both pins) to gnd with a 0.1 f f capacitor as close as possible to the device. 29, 57 29, 57 v ee v ee supply voltage. bypass v ee (both pins) to gnd with a 0.1 f f capacitor as close as possible to the device. 30 30 v gnb driver voltage supply output. connect a 1 f f capacitor to v nnb as close as possible to the device. 31 31 v gpb driver voltage supply output. connect a 1 f f capacitor to v ppb as close as possible to the device. 32, 36, 40 32, 36, 40 v ppb high-voltage positive supply input. bypass v ppb to gnd with a 0.1 f f capacitor as close as possible to the device. 34, 38, 42 34, 38, 42 v nnb high-voltage negative supply input. bypass v nnb to gnd with a 0.1 f f capacitor as close as possible to the device. 35 35 out8 pulser output 8 37 37 out7 pulser output 7 39 39 out6 pulser output 6 41 41 out5 pulser output 5 44, 48, 52 44, 48, 52 v nna high-voltage negative supply input. bypass v nna to gnd with a 0.1 f f capacitor as close as possible to the device. 45 45 out4 pulser output 4 46, 50, 54 46, 50, 54 v ppa high-voltage positive supply input. bypass v ppa to gnd with a 0.1 f f capacitor as close as possible to the device. 47 47 out3 pulser output 3 49 49 out2 pulser output 2 51 51 out1 pulser output 1 55 55 v gpa driver voltage supply output. connect a 1 f f capacitor to v ppa as close as possible to the device. 56 56 v gna driver voltage supply output. connect a 1 f f capacitor to v nna as close as possible to the device. 59 59 dinn4 digital signal negative input 4 (see the truth tables section) 60 60 dinp4 digital signal positive input 4 (see the truth tables section) 61 61 dinn3 digital signal negative input 3 (see the truth tables section) 62 62 dinp3 digital signal positive input 3 (see the truth tables section) 63 63 dinn2 digital signal negative input 2 (see the truth tables section) 64 64 dinp2 digital signal positive input 2 (see the truth tables section) 65 65 dinn1 digital signal negative input 1 (see the truth tables section) 66 66 dinp1 digital signal positive input 1 (see the truth tables section) ep exposed pad. connect ep to gnd. not intended as an electrical connection point. maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
24 detailed description the MAX14808/max14809 octal three-level/quad five- level, high-voltage (hv) pulser devices generate high- frequency, hv bipolar pulses (up to q 105v) from low- voltage control logic inputs for driving piezoelectric transducers in ultrasound systems. all eight channels have embedded overvoltage-protection diodes and inte - grated active return-to-zero clamp. both devices have embedded independent (floating) power supplies (fpss) and level shifters that allow signal transmission without the need for external hv capacitors. the MAX14808 also features eight integrated transmit receive (t/r) switches. the max14809 does not have the t/r switch function. the devices feature two modes of operation, an octal three-level pulser mode (with integrated active return- to-zero clamp) or a quad five-level pulser mode. in octal three-level pulser mode, each channel is controlled by two logic inputs (dinn_ /dinp_) and the active return to zero features half the current driving of the pulser, 1a (typ). in quad five-level pulser mode, each channel is controlled by three logic inputs and the active return to zero has the same current driving of the pulser, 2a (typ). the devices can operate both in clocked and transparent mode. in clocked mode, data inputs can be synchro - nized with a clean differential or single-ended clock to reduce phase noise associated with fpga output signals that are detrimental for doppler analysis. in transparent mode, the synchronization feature is disabled and output reflects the data input after an 18ns delay. both devices feature adjustable maximum current (0.5a to 2a) to reduce power consumption when full current capability is not required. the devices feature integrated grass-clipping diodes (with low parasitic capacitance) for receive (rx) and transmit (tx) isolations. both devices feature a damping circuit that can be activated as soon as the transmit burst is over. the damping circuit has a typical on-resistance of 500 i . it fully discharges the pulsers output internal node before the grass-clipping diodes. operation mode the devices have four operation modes: shutdown, octal three-level, quad five-level, and transmit disable. use the mode0 and mode1 inputs to select the operation mode. truth tables x = dont care. 0 = logic-low, 1 = logic-high. table 1. shutdown mode (mode0 = low, mode1 = low) table 2. octal three-level mode (mode0 = high, mode1 = low, v nna = v nnb , v ppa = v ppb ) inputs outputs dinn_ dinp_ out_ lvout_ (MAX14808 only) x x high impedance high impedance (t/r switch off) inputs outputs dinn_ dinp_ out_ lvout_ (MAX14808 only) 0 0 clamp on (damp off) t/r switch off (lvout_ = gnd) 1 0 v nna /v nnb (damp off) t/r switch off (lvout_ = gnd) 0 1 v ppa /v ppb (damp off) t/r switch off (lvout_ = gnd) 1 1 clamp on (damp on) t/r switch on maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
25 shutdown mode all channels are disabled, no transmission and reception is possible. this mode has the lowest power consumption. octal three-level mode the devices operate in eight independent channels. each channel can generate a three-level pulse. the high-side and low-side fet of each channel are capable of providing 2.0a current, while the clamp is capable of 1a current. quad dual mode the devices operate in four independent channels. each channel can generate a five-level pulse. the devices feature independent dual voltage supplies (v nna , v nnb , v ppa , and v ppb ) and can generate pulses between gnd, v ppa , and v nna or between gnd, v ppb , and v nnb . the high-side and low-side fet as well as the clamp of each channel are capable of providing 2.0a current. x = dont care, 0 = logic-low, 1 = logic-high. note 7: only three control inputs (dinnx, dinpx, dinny) are required for five-level, dual-mode operation. dinpy can be connected to gnd or v dd . 0 = logic-low, 1 = logic-high. table 3. quad five-level dual mode (mode0 = low, mode1 = high) (note 7) table 4. transmit disable mode (mode0 = high, mode1 = high) inputs outputs dinnx x = 1, 2, 3, 4 dinpx x = 1, 2, 3, 4 dinny y = 5, 6, 7, 8 dinpy y = 5, 6, 7, 8 outx = outy lvouty y = 1, 2, 3, 4 (MAX14808 only) lvouty y = 5, 6, 7, 8 (MAX14808 only) 0 0 x 0 high impedance (damp off) t/r switch off (lvout_ = gnd) t/r switch off (lvout_ = gnd) 0 0 x 1 clamp on (damp off) t/r switch off (lvout_ = gnd) t/r switch off (lvout_ = gnd) 0 1 0 x v ppb (damp off) t/r switch off (lvout_ = gnd) t/r switch off (lvout_ = gnd) 1 0 0 x v nnb (damp off) t/r switch off (lvout_ = gnd) t/r switch off (lvout_ = gnd) 0 1 1 x v ppa (damp off) t/r switch off (lvout_ = gnd) t/r switch off (lvout_ = gnd) 1 0 1 x v nna (damp off) t/r switch off (lvout_ = gnd) t/r switch off (lvout_ = gnd) 1 1 1 x clamp on (damp on) t/r switch on t/r switch off inputs outputs dinn_ dinp_ out_ lvout_ (MAX14808 only) 0 0 high impedance (damp off) t/r switch off (lvout_ = gnd) 1 0 high impedance (damp off) t/r switch off (lvout_ = gnd) 0 1 high impedance (damp off) t/r switch off (lvout_ = gnd) 1 1 high impedance (damp on) t/r switch on maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
26 table 5. current drive selection disable transmit mode all eight high-voltage transmit channels are disabled, no pulse transmission is possible. the t/r switch (MAX14808 only) can be turn-on (to receive low-voltage signals) or turn-off (for isolation). current capability selection the devices feature pulser current drive capability selec - tion. two control inputs (cc0, cc1) control the current drive capability (table 5). sync function the devices provide the ability to resynchronize all the data inputs by means of a clean clock signal. in ultrasound systems, the fpga output signals are often affected by a high jitter. the jitter induces phase noise that is detrimental in doppler analysis. the input clock can be either a differential signal or a single-ended signal running up to 160mhz. data are clocked in on the rising edge of the clk input (falling edge of clk ). connect clk to gnd for single-ended operation. the sync feature can be enabled or disabled by the sync control input. drive the sync input low to disable the synchroniza - tion function (no external clock signal). drive the sync input high to enable the synchronization function (with an external clock signal). figure 6 shows the simplified clk and clk inputs schematic. figure 6. simplified clk and clk inputs schematic inputs pulser output current (typ) cc0 cc1 0 0 2a 1 0 1.5a 0 1 1a 1 1 0.5a differential to single-ended conversion single-ended clock select 2:1 mux v dd 2.5ki 2.5ki 40ki 40ki clk reference voltage clk v cc v cc v cc maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
27 t/r switches (MAX14808 only) each channel features a low-power t/r switch. the t/r switch recovery time after the transmission is less than 1.2 f s. the t/r switches are controlled by the same pulser digital inputs (see the truth tables section). no dedicated input signals are required to activate/deactivate the t/r switches. the integrated t/r switches do not require any special timings and can operate synchronously with the digital pulser. to minimize the leakage current dur - ing transmission, its recommended to switch off the t/r switches 3 f s before the beginning of the transmit burst. grass-clipping diodes a pair of diodes in antiparallel configuration (referred to as grass-clipping diodes) is presented at each pulsers output. the diodes reverse capacitance is extremely low, allowing a perfect isolation between the receive path and the actual pulsers output stage. active damp circuit an active damp circuit is integrated between the internal pulser output node (before grass-clipping diodes) and gnd. the purpose of this circuit is to fully discharge the pulser output internal node so that the node is not left in high-impedance condition as soon as the transmit burst is over. this results in two main advantages: 1) the grass-clipping isolation is more effective. 2) suppression of any low-frequency oscillation of a node that could be detrimental for doppler mode performances. independent (floating) power-supply enable ( ldo_en ) the devices feature the ldo_en control input to enable/ disable the internal fpss. this allows the usage of external high-efficiency power supplies to save system power. this option must be considered only for special applications requiring extremely low power dissipation. the low power dissipation of the embedded fpss already meets power requirements in most of the cases. drive ldo_en low or leave unconnected to enable the internal fpss; drive ldo_en high to disable the internal fpss. thermal warning outputs the devices feature an open-drain thermal-protection output (thp). when the internal junction temperature exceeds +150 n c, the devices automatically enter shut - down mode and thp asserts. the devices reenter normal operation and the thp deasserts when the die temperature drops below +130 n c. power sequencing when using the embedded fpss ( ldo_en = low), the devices do not require any power-up/power-down sequence. when external fpss are used ( ldo_en = high), the conditions v gp_ > (v ee - 0.6v) and v gn_ < (v cc + 0.6v) must be satisfied during the entire power-up/power-down transients (see the electrical characteristics tables). applications information exposed pad and layout concerns the devices provide an exposed pad (ep) underneath the tqfn package for improved thermal performance. connect ep to gnd externally and do not run traces under the package to avoid possible short circuits. to aid heat dissipation, connect ep to a similarly sized pad on the component side of the pcb. this pad should be connected through to the solder-side copper by several plated holes to a large heat-spreading copper area to conduct heat away from the device. the devices high-speed pulser requires low-inductance bypass capacitors to their supply inputs. high-speed pcb trace design practices are recommended. pay particular attention to minimize trace lengths and use suf ficient trace width to reduce inductance. use of surface-mount components is recommended. typical application circuit figure 7 shows the MAX14808 in an octal three-level pulsing application. maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
28 figure 7. octal three-level pulsing (MAX14808) 18 20 19 21 22 23 24 25 26 27 28 29 30 31 gnd v dd dinp5 dinn5 8 dinn5?dinn8 dinp5?dinp8 4 4 lvout1?lvout4 analog front-end lvout5?lvout8 dinp6 dinn6 dinp7 dinn7 dinp8 dinn8 v cc v ee v gnb v gpb gnd v dd dinp1 dinn1 dinp2 dinn2 dinp3 dinn3 dinp4 dinn4 v cc v ee v gna v gpa v ppa gnd v nna 60 59 58 57 56 55 66 65 68 67 64 63 62 61 12 34 56 78 91 01 11 21 31 4 51 50 49 48 47 46 45 44 43 42 41 40 39 38 mode0 mode1 lvout5 lvout6 lvout7 lvout8 cc1 cc0 clk clk sync thp lvout4 lvout3 lvout2 lvout1 v ppb out6 v nnb out8 out7 v ppb out5 v nnb gnd v nna out4 v ppa out3 v nna out2 v ppa out1 15 16 17 37 36 35 32 v ppb 33 gnd 10v, 1f 10v, 1f 34 v nnb 54 53 52 ldo_en v dd v cc v ee +hv0 -hv0 8 dinn1?dinn5 dinp1?dinp5 10v, 1f 10v, 1f v dd v cc v ee +hv0 +hv0 -hv0 +hv0 -hv0 -hv0 +hv0 -hv0 +hv0 -hv0 MAX14808 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
29 functional diagram lvout_ lvout_ out_ out_ MAX14808 max14809 power supplies and digital pulser control circuit grass-cl ipping diodes t/ r switch (MAX14808 only) v gpa v nna v ee v cc v ppa v ds v ds v gna v nna v ppa v ppb v nnb v ee v cc gnd cc0 cc1 mode0 mode1 clk clk sync ldo_en dinn_ dinp_ gnd damp channels 1?4 gnd gnd gnd grass-cl ipping diodes t/ r switch (MAX14808 only) v gpb v nnb v ee v cc v ppb v ds v ds v gnb gnd damp channels 5?8 2 channels gnd gnd gnd maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
30 ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ** = future product. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part transmit channels t/r switches temp range pin-package MAX14808 etk+ yes yes -40c to +85c 68 tqfn-ep* max14809 etk+** yes no -40c to +85c 68 tqfn-ep* package type package code outline no. land pattern no. 68 tqfn-ep t6800+4 21-0142 90-0101 maxim integrated MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 31 ? 2012 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/12 initial release MAX14808/max14809 octal three-level/quad five-level high-voltage 2a digital pulsers with t/r switch

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